Total 457 Art / Design / Entertainment job vacancies in Northport, New York

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• Remove hair using permanent and temporary methods (e.g. electrolysis and waxing)
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• Give manicures and pedicures following clients’ preferences
• Recommend hairstyles and nail colors to match clients’ needs and personal style
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• Cross-sell therapies and beauty products, when relevant
• Make sure our working area is clean and equipment is sterilized at all times
• Keep track of levels of stock (e.g lotions and nail polis

Overall Summary:

Plan, design, develop and review infrastructure architectural solutions for on-prem/hybrid Cloud, throughout infrastructure lifecycles.

Roles & Responsibilities:

• Architect and design scalable and secure IT infrastructure, primarily on-premise as well as leveraging on cloud technologies, that is resilient, highly available and secured.

• Develop infrastructure solutions to meet project requirements and establish roadmaps, patterns, principles, standards and guidelines for on-prem infrastructure, and document them in various formats, diagrams and templates

• Validate, review and verify infrastructure aspects of project solutions and technical specifications, based on alignment with mandated enterprise policies and standards

• Own and drive architectural deliverables, working in close collaboration with stakeholders including Project Managers, Subject Matter Experts (SMEs) and vendors to achieve project outcomes and timelines from design to implementation.

• Assess new infrastructure technologies and participate in proof of concept, to assist in defining technology direction, roadmap, framework and policies to meet strategic business initiatives.

• Present, articulate and communicate deliverables including architecture related design, solutions, concepts, ideas and proposals to various stakeholders.

• Keep abreast of emerging trends and identify opportunities for improvement

• Review technical documentation including Technical Design Specs and VM Provisioning Requests

• The infrastructure scope covers, but not limited to, all aspects of cloud, servers, hypervisors, containers, operating systems, databases, middleware, devops, security, support tools, network, SDN as well as related governance framework.

Requirements / Qualifications

• Degree in Computer Engineering / Electrical and Electronic Engineering or equivalent discipline

• At least 7 years’ proven experience in a similar role

• Strong and in-depth technical knowledge and experience in administering and maintaining infrastructure domain areas such as Operating Systems (e.g., VMware, Nutanix, Red Hat, Windows Server), Networking (e.g., SDN, Cisco), Security (e.g. Cisco, Palo Alto,CheckPoint, F5), Automation (e.g., Ansible, Chef, Terraform), Cloud, etc.

• Certifications in the above areas would be advantageous (e.g. CCIE, CISSP, VMware VCAP, Windows Certified Engineer, RedHat Certified Engineer, AWS Solution Architect, Azure Solution Architect, TOGAF)

• Possess good knowledge of networks and networking concepts

• Possess good knowledge of ITIL processes

• Possess good knowledge on private, hybrid and public cloud environment and technologies which includes VMware vRealize Cloud automation, AWS, Azure and OpenShift

• Possess good security, audit and compliance knowledge

• Able to analyse and understand complex technical systems built from many separate software and hardware components, specifically web application architectures

• Strong passion for innovation and desire to learn new technologies

• Possess initiative, with a proactive, result-oriented mindset and able to work independently

• Track record of on-time, on-budget and to-specification delivery with the ability to support end-to-end delivery of solutions.

• Experience in driving complex IT infrastructure design and projects while optimizing costs

• Able to prioritise assignments whilst working on multiple concurrent projects

• Is meticulous and attentive to details

• A team player with Excellent communication, interpersonal and collaboration skills, capable of effectively communicating complex technical concepts and influencing various internal and external stakeholders, both technical and non-technical alike.

• 2 years contract

EDP Renewables APAC is the main subsidiary of EDP Group, a global leader in the renewable energy sector and one of the world’s largest wind producers. With its headquarters in Singapore, EDP Renewables is the leading sustainable development hub for the Asia Pacific region with activities across nine different markets. Our activities are focused on the design, development, management, and operation of renewable energy sources, namely solar, wind, as well as new technologies such as storage.

EDP is a global energy group leading the Energy Transition, Innovation and Sustainability. Using the technology of the future, we create solutions highly focused on the needs of our people and our customers, never neglecting our role and contributions to society. To achieve our goals, we aim to attract diverse people with high potential through the professional opportunities we create.

Join us to be part of a renewable energy leader that reinvests in society through sustainable projects and social as well as cultural causes. You will have the opportunity to actively participate in our global transformation, by changing tomorrow now.

The Senior Design Engineer is responsible for engineering and design of grid connected solar photovoltaic systems (including utility-scale and distributed generation projects). He/she will review solar system engineering designs, modelling, and performance data, and provide engineering support during the development and construction process.

Responsibilities:

• Conduct engineering site audits to collect structural, electrical and related site information for use in the design of commercial and utility-scale solar power systems
• Design and coordinate design of photovoltaic (PV) systems, including system components to suit site condition and in accordance to solar engineering standards (IEC, Singapore Standards etc)
• Design and develop electrical single-line diagram, panel schedules and connection diagram for solar electric systems using computer-aided design (CAD) software
• Prepare and follow up the Master Document Register (MDR)
• Perform solar energy production analysis from designed PV systems and seek to optimize efficiency through cost-benefits analysis
• Review specifications and recommend engineering or manufacturing changes to achieve solar design objectives.
• Evaluate plans or specifications to determine technological or environmental implications.
• Recommend technical design or process changes to improve efficiency, quality, or performance.
• Provide technical direction or support to Project Manager and Engineer during installation, start-up, testing, system commissioning, or performance monitoring.
• Create checklists for review or inspection of completed solar installation projects.
• Analyze costs and benefits of proposed designs or projects and performing cost reduction analyses for solar systems.
• Review of EPC’s Scope of Work, Specifications and comments on design and installation

Requirements:

• At least 3 years of commercial PV system design and engineering
• Bachelor's in Engineering (Mechanical, Electrical or related discipline preferred)
• Experience with low, medium and high voltage power electronics
• Competence in energy modelling software such as PVsyst is mandatory
• Competence in Autocad is mandatory
• Well versed in Microsoft Office, especially Excel
• Must be willing to learn and apply new technologies
• Knowledge of codes such as the IEC, Singapore Standards and construction practices
• Working knowledge of standard electrical calculations, basic structural & mechanical calculation

When you join EDP Renewables APAC, you will have access to:

• Professional experience in a leading global company in the renewables industry with flexible work conditions
• Recognition through remuneration compatible with the role and other additional benefits
• Opportunities for personal and professional development, e.g. cross-cutting projects, mobilities and volunteering

About EDP Group:
As a socially responsible company, we incorporate our values and practices with the principles of Diversity and Inclusion. To achieve all our objectives, we intend to attract, develop and retain different profiles, assuming diversity as a key factor and differentiator of fundamental innovation in our organisation. We welcome and value all people, and we are committed to the inclusion and sense of belonging of each person who is part of the EDP Group.

What makes us proud as an employer:
• TOP Employer APAC, Singapore 2024 certification
• TOP Employer Europe 2024 certification
• Bloomberg Gender Equality Index 2021
• Top Workplaces US 2021
• Certification in Conciliation (Excellence) by the Más Familia Foundation

Responsibilities:

• Gather, assess, refine, and translate business requirements into technology requirements.
• Design data architecture framework and standards for scalability, performance, high availability, and reliability throughout the data life cycle.
• Work closely with project team (business, solutioning and infrastructure, etc) throughout the project cycle.
• Define and govern data architecture artifacts.

Note: Proceeding to apply on this job post means you have read, understand and agreed to WPH DATA PROTECTION NOTICE FOR JOB APPLICANTS in the link below.

https://www.wphdigital.com/notices

Responsibilities:

• Design and develop AI/ML solutions: Lead the design and architecture of AI/ML systems, including selecting appropriate algorithms, models, and technologies to address specific business challenges.
• Technical leadership: Provide technical leadership and guidance to AI/ML development teams, ensuring best practices, scalability, and performance optimisation.
• Solution implementation: Oversee the end-to-end implementation of AI/ML projects, from data collection and preprocessing to model training, validation, and deployment.
• Collaboration: Collaborate with cross-functional teams, including data scientists, engineers, and business stakeholders, to understand requirements and translate them into AI/ML solutions.
• Research and innovation: Stay updated on the latest AI/ML trends, research, and tools, and apply innovative approaches to solve complex problems and drive continuous improvement.
• Performance evaluation: Evaluate the performance and accuracy of AI/ML models, and iterate on solutions to enhance predictive capabilities and business value
• Governance and compliance: Ensure adherence to data governance, privacy regulations, and ethical considerations in AI/ML solution development and deployment.

Note: Proceeding to apply on this job post means you have read, understand and agreed to WPH DATA PROTECTION NOTICE FOR JOB APPLICANTS in the link below.

https://www.wphdigital.com/notices

Job Description

• Working on 6nm and below advanced process project APR and Timing/PI sign-off
• Take the TOP and PM role for the complicated hierarchical chip (more than 20M inst plus 500+ macros)
• Take the Block or Block coordinator role for complex blocks
• Do early prediction for critical APR/Timing/PI issues

Job Requirements

• APR/Timing/PI hands-on/tapeout experience on complicated hierarchical chip
• TCL/Perl/Python/C/C++ programming skill
• Have advanced process(n6 or below) experience is a plus
• Excellent communication and team work spirit

Job description:

• Design Engineer for embedded memory design and verification in advanced nodes for high performance ASIC targeting Cloud AI/ Data Center Network Switch and 5G infrastructure, CPU and AP-SOC
• Collaborate closely with product and architecture teams to define, design and develop high performance customized semiconductor memories to meet PPA specifications and integration.
• Innovate, design, and incorporate special circuits and methodology to achieve best-in-class PPA for custom and compiler memories.
• Develop timing/power/noise characterization flow for advanced node memory compiler. Strong focus on design automation for SRAM compiler, big data analysis and design verification
• Develop memory analysis flow for PPA check

Job requirements:

• 3+ years of hands on experience in design of embedded memories (SRAM, TCAM) for high performance processors or ASICs in advanced nodes (3nm/5nm)
• Good understanding of Digital Circuit design techniques in FinFet technologies.
• Exposure to complete design cycle of SRAM memory and compiler development
• Supervise layout engineers and review layout for optimality.
• Experience in using industry standard schematic entry tools, advanced transistor level simulators (XA, HSIM, FINESIM)
• Experience with LEC tools (ESPCV)
• Knowledge of RTL and place and route tools is a plus
• Ability to come up with design verification and test plans
• Silicon debug and bring up experience is a plus
• Working knowledge of scripting in Perl/Python
• Willingness to collaborate closely with cross functional teams across the globe

The Job

• Develop timing/power/noise characterization flow for advanced node memory compiler.
• Strong focus on design automation for SRAM compiler, big data analysis and design verification.
• Develop memory analysis flow for PPA check.

The Talent

• Bachelor's Degree (with min. 6 years of relevant industry experience) /Masters Degree (with min. 4 years of relevant industry experience)/ PhD in Electrical and Electronic Engineering/Computer Engineering/Computer Science.
• Knowledge of SRAM/ROM memory functionality and high speed, low power memory design architecture.
• Experience in spice simulation and understand CMOS layout view, Verilog coding is preferable.
• Proficient in script programming with Perl or Python3.

Job Description

• Working on 6nm and below advanced process project APR and Timing/PI sign-off
• Take the TOP and PM role for the complicated hierarchical chip (more than 20M inst plus 500+ macros)
• Take the Block or Block coordinator role for complex blocks
• Do early prediction for critical APR/Timing/PI issues

Job Requirements

• APR/Timing/PI hands-on/tapeout experience on complicated hierarchical chip
• TCL/Perl/Python/C/C++ programming skill
• Have advanced process(n6 or below) experience is a plus
• Excellent communication and team work spirit

We are looking for a self-motivated candidate with expertise in high performance digital design and system level architecture modeling to join our Heterogeneous System design team. This candidate will work closely with IME’s advanced packing team and contribute to the exploration, optimization and development of multicore & multi-chip system using IME’s heterogeneous integration platform.

Job Description:

· Digital IC Design and system-level exploration:

o Lead and contribute to the design and development of digital integrated circuits, ensuring they meet performance and functionality requirements.

o <!-Emphasize a system-level perspective in the design process, considering overall system architecture and functionality.

o Apply a deep understanding of cryogenic temperature effects on digital ICs and implement design strategies for optimal performance in low-temperature environments.

o Incorporate Edge AI principles into digital IC designs, enabling efficient and intelligent processing at the edge of the network.

o RTL implementation for custom circuit design using Verilog/SystemVerilog

o Derive specs and implement necessary customized and highly efficient building blocks such as systolic array, data path controller, scheduler, integer and floating-point processing engine, FFT, etc which are frequency used in various computing architecture such as in-memory computing, deep learning and neuromorphic computing.

· Simulation, Verification, and Implementation:

o Conduct thorough simulation and verification of digital designs to validate functionality and performance.

o Utilize FPGA in digital IC designs, leveraging its flexibility and reconfigurability for system emulation and architecture exploration

o Perform timing analysis and collaborate with the team to optimize designs for timing closure.

o Contribute to power analysis activities and implement power-efficient design techniques.

Publish research works in prestigious conferences and Journals such as ISSCC, VLSI Symp, A-SSCC, DAC, JSSC and TCAS-I/II.

· Collaborate closely with cross-functional teams, including hardware and software engineers, to seamlessly integrate digital ICs into the overall system architecture.

· Prepare detailed design documentation, including specifications, test plans, and reports.

· Troubleshoot and debug digital IC designs with a focus on identifying and addressing system-level issues.

· Bring creative and innovative solutions to design challenges, staying abreast of industry trends and emerging technologies.

Requirements: Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. The candidate should have prior experiences in IC tape-out of digital/mixed signal SoC and system level modelling and optimization using industry standard tools from leading EDA vendors such as Cadence, Synopsis and Matlab.

• We are a chip design service company invested by an international consortium and founded by a senior chip design technical team.
• The company is headquartered in Singapore and will take root in Singapore for long-term development.
• In the future, we will also open branches in China, Japan and other places. The company has strong R&D capabilities and its core technical team members all have more than 10 years of experience in chip design.
• We have rich industry experience and deep practical accumulation in ASIC design and business management.

Our office is located in one North and walking distance from MRT.

We Provide competitive salary and compensation package for the right candidate.

Job Description：

1. Works with the front-end design team to complete the chip floorplan , clock architecture, and powerplan .

2. Takes charge of the physical design tasks from the Netlist to the GDSII, including P&R, formal verification, static timing analysis, physical verification, power analysis, design for reliability and tapeout.

3. Researches the physical design methodology of advanced process nodes, and builds an automatic physical design platform.

Position Requirements:

1. Holds a bachelor's degree or above in electronic engineering, microelectronics, or computer science.

2. At least 5 years of work experience in the digital backend design field. Hands-on project experience is required. Tapeout experience at advanced technology is prefered. ( for excellect junior candidates with 3+ years experience will be considerated )

3. Those with experience in TCL , Perl or Python script development and familiar with EDA tool design will be plus.

4. Strong communication ability, good confidence and self-movitation.

5. Bilingual and with good teamwork spirit.

6. Salary is negotiable for excellent candidates.

We are looking for a self-motivated candidate with expertise in high performance digital design and system level architecture modeling to join our Heterogeneous System design team. This candidate will work closely with IME’s advanced packing team and contribute to the exploration, optimization and development of multicore & multi-chip system using IME’s heterogeneous integration platform.

Job Description:

· Digital IC Design and system-level exploration:

o Lead and contribute to the design and development of digital integrated circuits, ensuring they meet performance and functionality requirements.

o <!-Emphasize a system-level perspective in the design process, considering overall system architecture and functionality.

o Apply a deep understanding of cryogenic temperature effects on digital ICs and implement design strategies for optimal performance in low-temperature environments.

o Incorporate Edge AI principles into digital IC designs, enabling efficient and intelligent processing at the edge of the network.

o RTL implementation for custom circuit design using Verilog/SystemVerilog

o Derive specs and implement necessary customized and highly efficient building blocks such as systolic array, data path controller, scheduler, integer and floating-point processing engine, FFT, etc which are frequency used in various computing architecture such as in-memory computing, deep learning and neuromorphic computing.

· Simulation, Verification, and Implementation:

o Conduct thorough simulation and verification of digital designs to validate functionality and performance.

o Utilize FPGA in digital IC designs, leveraging its flexibility and reconfigurability for system emulation and architecture exploration

o Perform timing analysis and collaborate with the team to optimize designs for timing closure.

o Contribute to power analysis activities and implement power-efficient design techniques.

Publish research works in prestigious conferences and Journals such as ISSCC, VLSI Symp, A-SSCC, DAC, JSSC and TCAS-I/II.

· Collaborate closely with cross-functional teams, including hardware and software engineers, to seamlessly integrate digital ICs into the overall system architecture.

· Prepare detailed design documentation, including specifications, test plans, and reports.

· Troubleshoot and debug digital IC designs with a focus on identifying and addressing system-level issues.

· Bring creative and innovative solutions to design challenges, staying abreast of industry trends and emerging technologies.

Requirements: Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. The candidate should have prior experiences in IC tape-out of digital/mixed signal SoC and system level modelling and optimization using industry standard tools from leading EDA vendors such as Cadence, Synopsis and Matlab.

Interested applicants are invited to apply directly at the NUS Career Portal

Your application will be processed only if you apply via NUS Career Portal

We regret that only shortlisted candidates will be notified.

About the Asian Institute of Digital Finance (AIDF)

The Asian Institute of Digital Finance (AIDF) is a university-level institute in the National University of Singapore (NUS), jointly founded by The Monetary Authority of Singapore (MAS), the National Research Foundation (NRF) and NUS. AIDF aspires to be a thought leader, a FinTech knowledge hub, and an experimental site for developing digital financial technologies as well as for nurturing current and future FinTech researchers and practitioners in Asia.

Duties and Responsibilities

• Work with the research team to build and enhance the existing IT infrastructure, related to Big Data and AI-powered digital finance research
• Build out the data pipeline that will feed into the research project
• Strong business analytics background
• Strong Mathematics background
• Strong programming skills in Python, Java and C++
• Full stack developing experience

Qualifications

• PhD in an IT or Computer Science related field
• At least 7 years of relevant experience designing and managing Big Data and Data Science infrastructure
• Strong analytical and problem-solving skills, with the ability to translate complex data into actionable insights.
• Excellent communication skills, including the ability to write reports and deliver presentations to a variety of stakeholders.
• Ability to work collaboratively in a team environment and manage multiple projects simultaneously

Job Duties

• Studying the requirements and developing an implementation strategy to transform the requirements into workable solutions,
• Guides the developer to ensure proper implementation and act as link between the project team and developers.
• Other key responsibilities include ensuring solution developed is cross-browser compatible, smooth integration with other systems, meets accessibility, usability and vulnerabilities guidelines, international best practices and government standards.

Skills and Qualifications

• Bachelor’s degree or other equivalent practical experience preferably in software engineering, computer science, or information technology
• The Solution Architect shall have FIVE (5) years relevant experience as a Solution Architect
• Candidate MUST HAVE a Solution Architect Certification (e.g.,Cloud Certification in Azure Solution Architect Expert or equivalent, Microsoft Certified Architect, Certified Enterprise Java Architect for J2EE platforms, SEI Software Architect Certification or IASA Certified IT Architect Profession or equivalent.)

Note: Proceeding to apply on this job post means you have read, understand and agreed to WPH DATA PROTECTION NOTICE FOR JOB APPLICANTS in the link below.

https://www.wphdigital.com/notices

Requirements:

1) A degree in Civil Engineering from a university or its equivalent that is recognized by the Professional Engineer Board, Singapore.

2) Minimum 6 years of design experience in Building projects and/or Earth Retaining Structures within a consulting environment.

3) Strong engineering analysis and design skills and knowledge.

4) Competent in common engineering design software and analytical tools.

5) Proficient or have experience in programming skills will be an advantage.

6) Conversant with relevant regulations and authority submissions and capable of leading the entire authority submission process.

7) Competent in precast concrete, post-tensioned concrete and steel works design.

8) Familiarity with MET and PPVC will be an added advantage.

9) Conversant with local codes and knowledge of the design codes in the region.

10) Capable of working independently, carrying out design, performing peer review or value engineering on structural solutions

11) Capable of leading the C&S design in a project.

12) Good planning, organizational, writing and communication skills.

Job Description :

1) Lead and perform Civil/Structural engineering analysis and design.

2) Perform hands-on design, provide technical input and ensure work quality is maintained at the expected standard in a project.

3) Participate in BIM coordination with the assistant of the BIM team.

4) Prepare technical specifications and manage projects.

5) Conduct feasibility study, engineering assessment and prepare technical report.

6) Carry out site inspections and technical reviews, when necessary.

7) Design management and participation in the successful delivery of projects.

8) Attend meetings, reporting and design matters.

9) Liaise with fellow Engineers and/or Consultant team.

If you are interested in joining us, please send your CV with the following information to vbpluse@singnet.com.sg or reply to the post.

1) CV including relevant experiences and nationality

2) Current and Expected salary