Total 2 job vacancies by Espressif Systems (singapore) Pte. Ltd.

Job responsibilities

1. Responsible for Physical Design for Full chip/Blocks covering Floor planning, Placement, Area Optimization, Clock tree synthesis, Placement optimizations, Routing, Timing Closure, power network design, Voltage drop analysis, RC extraction, etc.

2. Be a highly-valued member of our start-up like team through excellent collaboration and teamwork with other R&D Engineers.

3. Work with Frontend team to understand the RTL design and drive physical aspects early in design cycle for physical design closure.

Job requirements

1. Bachelor's degree or above, major in Microelectronics / Electronic engineering / Communication engineering and other related fields.

2. More than 3 years working experience in layout and wiring of 40 nm and below technology.

3. Able to independently complete the whole chip P&R process and IR_ Drop, STA, low power inspection.

4. Familiar with TCL or Perl and other scripting languages.

5. Familiar with design flows and EDA tool software.

6. Familiar with Sign-off methodology and the use of EDA tool software in STA / power.

This is an opportunity to be a key player at a company with a great reputation in IoT semiconductor technology and growing business. We are looking for experienced/senior engineers to join our team in Singapore and be involved to develop the next generation IoT/AI chips based on a revolutionary architecture.

1. Work with team to define the design of WIFI/BT related modules.
2. Develop RTL design of one or more blocks, define RTL module partition, timing requirement etc.
3. Work with multi-disciplinary groups to make sure designs are delivered on time and with highest quality by incorporating proper checks at every stage of the design process.
4. Assist with the development of company documentation and generation of patents.

Qualification

1. Master's degree in Electrical Engineering (or equivalent), with 5+ years’ industry experience.
2. Team player, with good problem solving and communication skills.
3. Proficiency in System Verilog for RTL logic design and verification.
4. Familiarity with the design of digital MAC/baseband/high-speed interface/CPU or DSP is a plus.
5. Experience in Architecture/Block definition for SOC system such as WiFi, Bluetooth and GNSS.
6. Experience in micro-architecture design, and RTL coding with Verilog, familiar with Cadence and Synopsis tools.
7. Experience in synthesis, with analysis of power, timing and area.
8. Review micro-architecture to meet specification requirements and perform Design Quality Check
9. Experience in RTL and gate level simulation, unit test, system test and EDA verification