Total 4 job vacancies by Curious Tek Pte. Ltd.

Job Responsibilities:

• Develop digital and analog layout in various technologies (e.g., CMOS )
• Layout analog circuits and IO circuits
• Analyse and rectify layout verification issues
• Support the front-end team for System-on-Chip (SoC) integration

Requirements:

• Possess at least a bachelor’s degree or equivalent in Electrical & Electronic Engineering or any related field with background on Integrated Circuit Design (both Analog and Digital)
• 5 years or above experience in the area of layout design.
• Knowledge in Electronic Design Automation (EDA) tools (e.g. Cadence, Synopsys, Mentor Graphic Calibre)
• Knowledge in circuit reliability consideration for layout (e.g., ESD, latch-up, aging, EMIR)
• Able to trouble-shoot and rectify layout verification error on DRC/LVS and familiar with layout signoff flow.
• Strong Communication skills, high level of independence, self-motivation and a good team player.

Job Responsibilities:

· Design and implementation of mixed signal CMOS IP. Development cycle including circuit design, simulation, modeling, verification and bench characterization.

· Management products utilizing leading edge sub-micron CMOS technologies, e.g., 5/6nm

· Developing state of the art high speed mixed signal IP products that include op amps, comparators, bandgap, low-drop linear regulator, ADCs, DC-DC converters, and high bit-rate (Gbps) Serdes TX/RX.

Requirements:

· Bachelor or above degree in Microelectronic or Electronic and Information Engineering

· 5 years or above experience in the area of analog design

· Good knowledge in analog IC design in high speed Serdes, e.g., PLL, CDR, CTLE/DFE, TX driver etc.

• Solid understanding and experience in key analog layout considerations such as device matching, parasitic, noise coupling, floor planning, sensitive signal routing, current density and reliability considerations
• Familiar with SPICE simulation tool (e.g., Cadence spectre, Synopsys Custom Compiler, Calibre)

· Strong Communication skills, high level of independence, self-motivation and good team player

Job Responsibilities:

· Manage a team of analog layout engineers, providing leadership, mentorship, and technical guidance.

· Oversee the layout design, and verification in technologies such as CMOS etc.

· Collaborate with design and PD teams to translate circuit designs into physical layouts.

· Ensure the team meets project schedules and deliverables, maintaining the highest quality standards.

· Conduct layout reviews to ensure design compliance with specifications and adherence to industry best practices.

· Coordinate with cross-functional teams for debugging, yield improvement, and issue resolution.

· Contribute to layout process and methodology improvements and automation.

· Stay updated with the latest technology trends and advancements in the field of analog layout design.

Requirements:

· Bachelor’s or Master’s degree in Electrical Engineering or related field.

· Minimum of 7 years of experience in analog layout design with at least 2 years in a management or team lead role.

· Proficiency in industry-standard EDA tools such as Cadence Virtuoso, Synopsys Custom Compiler and Mentor Graphic Calibre.

· Deep understanding of semiconductor physics, device fabrication processes, and layout techniques.

· Experience in managing layout designs for a variety of analog circuits, including power, high speed, mixed signal, etc.

· Exceptional leadership skills with a proven ability to manage and develop a high-performing team.

· Strong analytical skills with the ability to solve complex technical problems.

· Excellent communication skills with the ability to clearly articulate technical concepts.

· Experience with advanced FinFET process nodes e.g., TSMC 5/6nm.

Job Responsibilities:

· Design and implementation of mixed signal CMOS IP. Development cycle including circuit design, simulation, modeling, verification and bench characterization.

· Management products utilizing leading edge sub-micron CMOS technologies, e.g., 5/6nm

· Developing state of the art high speed mixed signal IP products that include op amps, comparators, bandgap, low-drop linear regulator, ADCs, DC-DC converters, and high bit-rate (Gbps) Serdes TX/RX.

Requirements:

· Bachelor or above degree in Microelectronic or Electronic and Information Engineering

· 5 years or above experience in the area of analog design

· Good knowledge in analog IC design in high speed Serdes, e.g., PLL, CDR, CTLE/DFE, TX driver etc.

• Solid understanding and experience in key analog layout considerations such as device matching, parasitic, noise coupling, floor planning, sensitive signal routing, current density and reliability considerations
• Familiar with SPICE simulation tool (e.g., Cadence spectre, Synopsys Custom Compiler, Calibre)

· Strong Communication skills, high level of independence, self-motivation and good team player