Total 3 Internship art design entertainment job vacancies in San Francisco

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The Cadence Silicon Solutions Group (SSG) is seeing rapid adoption of our industry leading Digital IP (intellectual Property), from processor cores and DSPs to Memory Controllers and IO solutions. Our configurable and extensible IP solutions are poised to meet the demands of intelligent IoT Devices at the edge of ML/AI Applications. We are already empowering many of the top chip and system companies with our Silicon Solutions.

Cadence SSG Team is hiring students to join our R&D teams in San Jose or Austin. This is an amazing opportunity to work at a world leader in computational software, semiconductor design IP, and system verification hardware.  Our customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare.

Come be part of this great SSG Team where you can make an impact that is visible.  

Design Engineering Intern positions are for one of two roles:
(a) Perform as a member of the Logic Design Team on a Digital Design project such as an L2 Cache or a Network on Chip project. Responsible for the RTL implementation of high performance memory system and interconnect components. Implement the micro-architecture in Verilog RTL, simulate and debug its functions and run synthesis, place & route and other Electronic Design Automation scripts to meet timing, area, and power goals. Assist with developing test plans; writing functional diagnostics; debugging failures; and analyzing coverage information. Work closely with various Design Verification and Electronic Design Automation teams.
(b) Perform as a member of the Design Verification Team on a Digital Design project such as an L2 Cache or a Network on Chip project. Responsible for verification of high performance memory system and interconnect components. Assist with developing test plans, writing functional assembly diagnostics, UVM/SVA monitors, debugging failures, and analyzing coverage information. Work closely with various RTL Design and Electronic Design Automation teams.

Position Requirements:
• Currently enrolled as MS/BS in Electrical Engineering, Computer Engineering, or a similar major.
• Deep understanding of Digital Design and/or Design Verification Fundamentals
• Excellent automation skills using Tcl, Perl, shell scripting
• Excellent oral and written communications skills
• Exposure to design automation tools is a plus

We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Design Engineering Intern

The Cadence Tensilica Processor Team is seeing rapid adoption of our industry leading processor cores and DSP's. Our configurable and extensible processor cores are poised to meet the demands of intelligent IoT Devices at the edge of ML/AI Applications. We are already empowering many of the top chip and system companies with our Audio, Speech, AR/VR, ADAS, Vision and Imaging applications being driven with our processor cores. Today Cadence is shipping an astounding 8 Billion processor cores annually and expanding into intelligent system design and development.

Cadence Tensilica Processor Team is hiring graduates to join our R&D teams in San Jose and Austin. This is an amazing opportunity to work as a Graduate Engineer at a world leader in computational software, semiconductor design IP, and system verification hardware.  Our customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare.

Come be part of this great Processor team where you can make an impact that is visible.  

Design Engineering Intern positions are for one of the three roles:
(a) Perform as a member of the Logic Design Team for Xtensa processors. Responsible for the RTL implementation of microprocessor cores, multiprocessor sub-systems and their peripherals. Implement the micro-architecture in Verilog RTL, simulate and debug its functions and run synthesis, place & route and other Electronic Design Automation scripts to meet timing, area, and power goals. Assist with developing test plans; writing functional diagnostics; debugging failures; and analyzing coverage information. Work closely with various Design Verification and Electronic Design Automation teams.
(b) Perform as a member of the Design Verification Team for Xtensa processors. Responsible for verification of microprocessor cores, multiprocessor sub-systems and their peripherals. Assist with developing test plans, writing functional assembly diagnostics, UVM/SVA monitors, debugging failures, and analyzing coverage information. Work closely with various RTL Design and Electronic Design Automation teams.

(c) Perform as a member of the Functional Safety Team for Xtensa processors. Responsible for Functional Safety features verification of microprocessor cores leading to certification for deployment of the cores in Automotive or Industrial systems. Assist with developing fault injection, writing functional assembly diagnostics, debugging failures, and analyzing coverage information. Work closely with various RTL Design teams.

Position Requirements:
• MS/BS in Electrical Engineering, Computer Engineering, or a similar major.
• Deep understanding of Digital Design and/or Design Verification Fundamentals
• Excellent automation skills using Tcl, Perl, shell scripting
• Excellent oral and written communications skills
• Exposure to design automation tools is a plus

We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Perform as a member of the Logic Design Team for Xtensa DSP Hardware group. Responsibilities include:

• Design and implement micro-architecture for DSPs, sub-systems and their peripherals.
• Simulate and debug the design.
• Run synthesis, place & route and other Electronic Design Automation scripts to meet timing, area, and power goals.
• Assist with developing test plans, debugging failures; and analyzing coverage information.
• Work closely with various Design Verification and Electronic Design Automation teams.
• Self-starter,  motivated and eager to learn and participate in the development of state of the art DSP products.

Requirements:

Currently pursuing BSEE or MSEE or equivalent.

We’re doing work that matters. Help us solve what others can’t.