Total 50 Internship job vacancies in San Francisco, California

• Review Appeals of adverse decisions on patent applications made by patent examiners;
• Review Appeals of Reexaminations and Reissue proceedings;
• Conduct Interference proceedings;
• Conduct Derivation proceedings; and
• Conduct AIA trials, including Inter Partes Review and Post-Grant Review.

• You enjoy reviewing arguments and evidence provided in motions, briefs, and oral hearings;
• You effectively work with colleagues to analyze and decide legal and factual issues;
• You are committed to preparing and issuing timely, high-quality decisions, that are consistent with statutes, regulations, case law, and agency policies;
• You reflect professionalism and judicial decorum; and
• You thrive by performing any task that supports the mission of the USPTO and the PTAB, such as: participating in stakeholder engagement, leading project teams, contributing to policy development, and developing best practices.

• You will apply analytical and evaluative methods to research program information, interpret guidelines and resolve procedural problems or issued, or make recommendations for process improvements that have a widespread impact.
• You will be responsible for ensuring all pay and allowances are calculated, submitted, and tracked for each individual student (training, travel, lodging, health care, and payments).
• You will be responsible for authorizing changes to orders, payments, and travel arrangements; processing and coordinating a wide variety of transactions through the disbursing office.
• You will create, monitor, analyze and update formal school schedule within a database system; ensure schedule information is correct by validating against Course Descriptive Data and Programs of Instruction.

*We accept applications for these occupations on an ongoing basis; qualified applicants will be considered as vacancies become available.

This announcement covers vacancies in multiple units/clinics within the Long Beach VA Healthcare System, to include: Outpatient Mental Health Division; Mental Health Residential Rehabilitation Program (MHRRTP); Community Living Center Skilled Nursing and Rehabilitation Unit; Home Based Primary Care (HBPC); Home Telehealth; Caregiver Support Program; Community Nursing Home; Non-Institutional Care (NIC) Program; Community Care; Homeless PACT; Patient Aligned Care Team (PACT)/Primary Care; Surgical/OR (3B); Emergency Department (ED); Medicine Sub-Specialty Clinics; Specialties & Diagnostics: Pre & Post-Operative Care; Spinal Cord Injury; Nurse Educator; Quality/Safety/Value; Inpatient Medicine and other Specialty Areas. Please Note: Anaheim, Cabrillo (Villages), Gardena, Laguna Hills, Santa Ana and Santa Fe Springs are Community Based Outpatient Centers (CBOC).

As a Staff Nurse you will provide prescribed medical treatment and personal care services to ill and injured veterans. Duties include documenting observations, assessments, and changes in patient's condition; collaborating with health team members to facilitate positive patient care outcomes; providing a full range of nursing care to patients with a variety of physical and/or behavior problems; and accountable for meeting and maintaining the qualification standards and functional statements of assigned grade. Our facility is seeking individuals who possess good organizational skills which enable completion of work, a demonstrated ability to assume leadership in a patient centered program, and the ability to establish effective communication with patients, families, visitors and members of the interdisciplinary team. Incumbent leads by example in defining a customer service culture to ensure that all customers are treated with respect and civility. Ensures that whenever possible works to cultivate partnerships with our customers in developing solutions to meet their needs.

VA offers a comprehensive total rewards package: VA Nurse Total Rewards

Pay: Competitive salary, regular salary increases, potential for performance awards
Paid Time Off: 50 days of paid time off per year (26 days of annual leave, 13 days of sick leave, 11 paid Federal holidays per year)
Retirement: Traditional federal pension (5 years vesting) and federal 401K with up to 5% in contributions by VA
Insurance: Federal health/vision/dental/term life/long-term care (many federal insurance programs can be carried into retirement)
Licensure: 1 full and unrestricted license from any US State or territory

Work Schedule: Full-time, part-time (part time hours range 8 to 72 per pay period), PRN, and intermittent. Assigned schedule corresponds to specific clinic (Some clinics require days, nights, weekends, rotating shifts and holidays).

Telework: not available
Virtual: This is not a virtual position.
Relocation/Recruitment Incentives: not authorized
Permanent Change of Station (PCS): not authorized

As a Program Coordinator (International Alumni Programs) at the GS-0301-12 some of your typical work assignments may include:

• Serve as a Program Coordinator (International Military Alumni Programs) in the planning, coordination, implementation, and management of activities and requirements in support of the establishment, development, and sustainment of ISG alumni engagement activities.
• Plan and oversee a Foundations of Fellowship Program that serves as a complimentary role to the academic program offered by ISG.
• Evaluate and monitor effectiveness of program, identify problems, and recommend improvements and changes.
• Initiate and maintain contact with ISG alumni and alumni organizations, for the purpose of developing and expanding networks.
• Promote and foster alumni relations through written communication and personal contact with alumni.
• Develop written materials designed to convey information concerning the institution's alumni programs and functions to external audiences and the public.

As a Program Coordinator (International Alumni Programs) at the GS-0301-12 some of your typical work assignments may include:

• Serve as a Program Coordinator (International Military Alumni Programs) in the planning, coordination, implementation, and management of activities and requirements in support of the establishment, development, and sustainment of ISG alumni engagement activities.
• Plan and oversee a Foundations of Fellowship Program that serves as a complimentary role to the academic program offered by ISG.
• Evaluate and monitor effectiveness of program, identify problems, and recommend improvements and changes.
• Initiate and maintain contact with ISG alumni and alumni organizations, for the purpose of developing and expanding networks.
• Promote and foster alumni relations through written communication and personal contact with alumni.
• Develop written materials designed to convey information concerning the institution's alumni programs and functions to external audiences and the public.

Performs administrative and reportorial tasks on Warehousing and Logistics processes in a BASCo Distribution Center. 

What You'll Do

• Assist in organizing and facilitating employee engagement activities and events.
• Support initiatives aimed at improving employee morale and satisfaction.
• Assist in organizing and facilitating employee events and activities.
• Assist with posting job openings and screening resumes.
• Coordinate training sessions and development programs.
• Help organize and support employee programs.
• Assist with day-to-day HR operations and tasks. C

• Currently pursuing a degree in Human Resources, Psychology, or a related field.
• Strong verbal and written communication skills.
• Excellent interpersonal skills with a focus on employee engagement.
• Basic knowledge of HR principles and practices.
• Proficient in using Microsoft Office Suite.
• Willing to work on a Face to Face Work setup and has a personal laptop
• Availability for voluntary or involuntary internship.
• Ability to commit a minimum of 600 hours or 3 months.
• Exudes Teleport Core Values • And a passion for Teleport's mission!

Job Summary

To support our extraordinary teams who build great products and contribute to our growth, this Summer, we’re looking to add a Software Developer Intern located in our Milpitas, CA site.

Reporting to the Special Projects Director, the student will be working on challenging projects in support of real-time business issues while developing skills and experiences.

What a typical day looks like:

• Manage and take full technical ownership of various projects
• Designing scalable web applications
• Assisting with technical design, and implementation of best practices and processes
• Building, testing, deploying and provisioning automation scripts to replace routine and repetitive tasks (from bug testing to operations)
• Collaborating closely with other project teams, solution architects, and hands-on developers to ensure that all DevOps strategy and objectives are aligned across teams
• Attend team meetings and support project work as needed

Student qualities we’re seeking for this internship assignment:

• Jr/Sr level undergrad pursuing Computer Engineering degree or related major
• Highly collaborative, creative and excellent communication skills
• Effective organizational, analytical and problem-solving skills
• Strong verbal, presentation and written communication skills
• Ability to work in teams and collaborate with others
• Self-motivated, high energy and strong time management skills
• Previous internship experience a plus!

Internship Program Requirements:

• Available to work 40 hours/week (in-person) for 10-12 week Summer assignment
• Currently enrolled in 4-year accredited university
• 3.0 minimum GPA

Job Category

Is Sponsorship Available?

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Working with the Cadence Tensilica XPG group to

• Develop a Java/Groovy program that transforms configurable processor descriptions from an internal model into alternate representations using templates with embedded language constructs.
• And also build a test harness to verify that the resulting transformations are correct.

Requirements:

• Currently enrolled in BS or MS in CS, CE, or equivalent.
• Core java data structures and algorithms
• Software engineering practices and source control systems
• Automation techniques for broad testing of transformation
• Ideally also 
  • server based web page generation for transformation output
  • SQL database knowledge for recording / reporting test data

We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

About Cadence: Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design™ strategy to deliver software, hardware, and IP that turn design concepts into reality. Cadence® customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. Fortune magazine has named Cadence one of the 100 Best Companies to Work For for nine years in a row.

About the Global Strategic Sourcing (GSS) organization: We are about People. Partnership. Performance. We provide strategic value in Cadence’s procurement process that includes spend visibility, sourcing, contract management, operations, and supplier management. Procurement proactively delivers a simplified and efficient solution that improves our customers' experience while ensuring compliance/risk mitigation and identifying cost savings opportunities.

At Cadence, we hire and develop leaders and innovators who want to impact the world of technology.

We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

About Cadence: Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design™ strategy to deliver software, hardware, and IP that turn design concepts into reality. Cadence® customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. Fortune magazine has named Cadence one of the 100 Best Companies to Work For for nine years in a row.

About the Global Strategic Sourcing (GSS) organization: We are about People. Partnership. Performance. We provide strategic value in Cadence’s procurement process that includes spend visibility, sourcing, contract management, operations, and supplier management. Procurement proactively delivers a simplified and efficient solution that improves our customers' experience while ensuring compliance/risk mitigation and identifying cost savings opportunities.

At Cadence, we hire and develop leaders and innovators who want to impact the world of technology.

We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

You will be a member of the team responsible for optimizing Neural Networks for Tensilica DSPs and hardware accelerators. You will gain familiarity with the Tensilica NeuroWeave Neural Network Compiler and use your knowledge to optimize Neural Network applications for Tensilica processors/accelerators.

Required Skills: 

* Understanding of neural network architectures, applications and accuracy evaluation

* Familiarity with neural network optimization techniques such as quantization (post training and qantization aware)

* Expertise in NN frameworks such as Tensorflow and Pytorch

* Good programming skills in programming languages such as C++ and Python

* The ideal candidate would be working towards a Master’s or PhD in Computer Science/Engineering or Electrical Engineering or related field

We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The Cadence Silicon Solutions Group (SSG) is seeing rapid adoption of our industry leading Digital IP (intellectual Property), from processor cores and DSPs to Memory Controllers and IO solutions. Our configurable and extensible IP solutions are poised to meet the demands of intelligent IoT Devices at the edge of ML/AI Applications. We are already empowering many of the top chip and system companies with our Silicon Solutions.

Cadence SSG Team is hiring students to join our R&D teams in San Jose or Austin. This is an amazing opportunity to work at a world leader in computational software, semiconductor design IP, and system verification hardware.  Our customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare.

Come be part of this great SSG Team where you can make an impact that is visible.  

Design Engineering Intern positions are for one of two roles:
(a) Perform as a member of the Logic Design Team on a Digital Design project such as an L2 Cache or a Network on Chip project. Responsible for the RTL implementation of high performance memory system and interconnect components. Implement the micro-architecture in Verilog RTL, simulate and debug its functions and run synthesis, place & route and other Electronic Design Automation scripts to meet timing, area, and power goals. Assist with developing test plans; writing functional diagnostics; debugging failures; and analyzing coverage information. Work closely with various Design Verification and Electronic Design Automation teams.
(b) Perform as a member of the Design Verification Team on a Digital Design project such as an L2 Cache or a Network on Chip project. Responsible for verification of high performance memory system and interconnect components. Assist with developing test plans, writing functional assembly diagnostics, UVM/SVA monitors, debugging failures, and analyzing coverage information. Work closely with various RTL Design and Electronic Design Automation teams.

Position Requirements:
• Currently enrolled as MS/BS in Electrical Engineering, Computer Engineering, or a similar major.
• Deep understanding of Digital Design and/or Design Verification Fundamentals
• Excellent automation skills using Tcl, Perl, shell scripting
• Excellent oral and written communications skills
• Exposure to design automation tools is a plus

We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Design Engineering Intern

The Cadence Tensilica Processor Team is seeing rapid adoption of our industry leading processor cores and DSP's. Our configurable and extensible processor cores are poised to meet the demands of intelligent IoT Devices at the edge of ML/AI Applications. We are already empowering many of the top chip and system companies with our Audio, Speech, AR/VR, ADAS, Vision and Imaging applications being driven with our processor cores. Today Cadence is shipping an astounding 8 Billion processor cores annually and expanding into intelligent system design and development.

Cadence Tensilica Processor Team is hiring graduates to join our R&D teams in San Jose and Austin. This is an amazing opportunity to work as a Graduate Engineer at a world leader in computational software, semiconductor design IP, and system verification hardware.  Our customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare.

Come be part of this great Processor team where you can make an impact that is visible.  

Design Engineering Intern positions are for one of the three roles:
(a) Perform as a member of the Logic Design Team for Xtensa processors. Responsible for the RTL implementation of microprocessor cores, multiprocessor sub-systems and their peripherals. Implement the micro-architecture in Verilog RTL, simulate and debug its functions and run synthesis, place & route and other Electronic Design Automation scripts to meet timing, area, and power goals. Assist with developing test plans; writing functional diagnostics; debugging failures; and analyzing coverage information. Work closely with various Design Verification and Electronic Design Automation teams.
(b) Perform as a member of the Design Verification Team for Xtensa processors. Responsible for verification of microprocessor cores, multiprocessor sub-systems and their peripherals. Assist with developing test plans, writing functional assembly diagnostics, UVM/SVA monitors, debugging failures, and analyzing coverage information. Work closely with various RTL Design and Electronic Design Automation teams.

(c) Perform as a member of the Functional Safety Team for Xtensa processors. Responsible for Functional Safety features verification of microprocessor cores leading to certification for deployment of the cores in Automotive or Industrial systems. Assist with developing fault injection, writing functional assembly diagnostics, debugging failures, and analyzing coverage information. Work closely with various RTL Design teams.

Position Requirements:
• MS/BS in Electrical Engineering, Computer Engineering, or a similar major.
• Deep understanding of Digital Design and/or Design Verification Fundamentals
• Excellent automation skills using Tcl, Perl, shell scripting
• Excellent oral and written communications skills
• Exposure to design automation tools is a plus

We’re doing work that matters. Help us solve what others can’t.