Total 12 job vacancies by Cadence

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

• Functional Verification Engineer for DDR Memory Controller and Phy IP development team.
• The role would include functional verification of the DDR Memory Controller and Phy IP solution of Cadence.
• The work involved will be working with the existing functional verification environment, addition of new features into the verification environment, ensuring various customer configurations are clean as part of verification regressions, supporting customers in case of any issues with using the verification environment, and functional and code coverage.
• The engineer would be responsible to ensure that the design is in line with the technical and quality requirements set for the team – particularly with respect to functional and code coverage.

Position Requirements:

• BS/MS - Electrical/Electronics/VLSI
• Strong background on Digital design and functional verification fundamentals
• Exposure/expertise in System Verilog and UVM based functional verification environment development is required.
• Scripting knowledge will be a plus.

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Description

- Work closely with the sales team to identify and scope opportunities for the Cadence Palladium platform.

- Understand the Goal and Objective, then plan and execute and manage key technical evaluations by co-working proactively with existing and potential customers as well as team colleagues

- Summarize the tasks and projects, and report to manager and share with team effectively

- Train, ramp-up and accompany customer project.

- Conduct basic and advanced trainings, presentations and demos as necessary.

- Ramp-up other members of the team on the advanced PXP/Emulation/Acceleration technologies and tools.

Requirement

- The candidate should possess minimum BS level of CS or EE with 10+ years of industry experience

- Minimun 7+ years experiences in Verification/Prototyping and consumer application design/debugging by EDA solution.

- Hands-on experience on SOC Emulation/Acceleration, Hybrid solution, UVM, Verification IPs or Transactors a big plus

- Familiar with Simulator (IES, VCS, etc) and some experiences of emulator/accelerators (PXP, Zebu, Veloce).

- Knowledge of Linux and tcl is a must

- Good program/engagement management skill

- Effective team player and good relationship with co-workers, willing to learn

- Experience of PCIe, UFS, NVMe, CHIe protocol

- Good communication skills in English and a strong desire for working in a global environment with customers and BU people

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

In this role, the Senior Account Executive is responsible for developing and driving a business strategy that leads to adoption and growth of the Cadence Systems Solutions which include Allegro PCB, IC Packaging and multi-physics analysis in their respective territory. Location is the UK, plus additional tasks relating to the automotive sector.

Justification

This is a new req to replace a position within the UK due to a change in role. This will be a Sr. AX role covering the UK SST Accounts and Automotive across EMEA for the Systems Sales Team.

Job Description

As a Senior Account Executive focused on the UK and Automotive Sector across EMEA Region, you will utilize your technical knowledge, deep insight of the Customer, and broader Industry knowledge to maximize and monetize the value of Cadence solutions which include Allegro PCB, IC Packaging and multi-physics analysis.  You will take responsibility of business-lines affiliated with technology domains and/or teams, develop the strategy and be accountable for execution while working with the wider Cadence team of both field and factory personnel.  You will need to rely on your relationships, knowledge, and superior communication skills to connect with business and technology customer stakeholders, identify critical customer challenges and gain buy-in to drive new business.

Key Qualifications

• Must be comfortable in a technical setting and have an understanding of EDA tools, Systems/PCB/IC design and the semiconductor manufacturing eco-system.
• Must have ability to call “high” (Executive and Engineering Management) and help drive multi-million dollar, complex sales campaigns with multiple decision makers and influencers across the customer organization.
• A comprehensive network within the automotive sector across EMEA driving our internal initiatives supporting the move from IC to EV, along with experience from OEM, Tier 1, and the wider supply chain.
• Deep understanding of electronics systems and IC software design processes relevant to the customer ecosystem.
• The ability to foster and grow customer relationships throughout all levels of the customer organization to better connect our solutions with the customer's problems/business challenges and insure roadmap alignment for long term success.
• A proven track-record demonstrating ability to identify and understand customer pain-points and the ability to communicate this to a broad range of technical and non-technical persons.
• Knowledge and demonstration of the ability to manage the complete sales process, strong communication skills, and the ability to interact with engineering and financial staff at all levels.
• A track record successfully managing multiple priorities, working with, and managing cross functional teams, and driving results as evidenced by overachievement of sales goals.
• Previous experience with Allegro, Mentor, Zuken, Altium or Ansys, Keysight

Position Requirements:

Experience

7+ years of professional experience in the electronics design business.

Verifiable track record of overachieving multimillion dollar sales quotas.

Education

MSc or BSc Degree in technical discipline, preferably EE.

MBA is a plus

Location

UK - working from home/Bracknell office.

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Responsibilities:

• Work closely with the account teams to scope out services project. Create a Statement of Work (SOW) and cost plans in collaboration with the technical leads and other organizations within Cadence including Cadence Finance and Legal.
• Lead cross-functional teams, ensuring that all deliverables are successfully managed, executed, monitored and controlled such that Customer success and satisfaction are achieved
• Creation, maintenance and tracking of project plans and schedules, activities and issues associated with customer engagement(s).
• Drive project tasks to completion in accordance with schedule, scope and cost constraints. Reports status and other metrics related to the project activity.
• Proactively identify, mitigate and resolve issues.
• Manage and set priorities for resources across teams to achieve project objectives.
• Foster an environment of collaboration, trust, and accountability for teams supporting the project while providing leadership, guidance and motivation to the cross-functional team while resolving internal conflicts.
• Contribute to best practices and efficiency improvements operations/processes.

Position Requirements:

Requires a Bachelor’s degree in electrical or computer engineering with a minimum of 7-10 years of experience. The ideal candidate possesses experience driving tactical services engagements and initiatives involving customer requests for analog, SOC, verification or package/board expertise. Background in IC design, SOC verification, RTL or IP development along with project management certification considered a plus.  Proven ability to manage multiple complex projects along with strong communication / presentation, assessment and analytical skills a must. Experience with Cadence design tools is a plus but not a requirement. Occasional domestic and internal travel is required for this position. 

The annual salary range for San Jose, CA is $ 134,400 to $249,600. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We offer amazing opportunities to grow, no matter where you are in your career.

The ideal candidate will be energetic, innovative and enthused with how to help customers, solve their toughest Digital Implementation problems using Cadence technology. Will drive Pre-sales and Post–sales activities at advanced nodes for Cadence Digital IC products.

Key Responsibilities

• Provide technical support to Cadence customers in the areas of Digital Design Implementation & Signoff including Synthesis, Place and Route, Design Closure, and timing/power signoff
• Guide customers on how to best utilize Cadence technologies to achieve their design goals and meet project schedules
• Conduct technical presentations and product demonstrations
• Drive technical evaluations/benchmarks to success
• Work closely with R&D to enhance the tools and methodologies to meet and exceed customer’s requirements
• Drive adoption and proliferation of Cadence tools and technologies
• Amend and augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows
• Capture best practices and lessons learned from current evaluations/benchmarks and utilize to improve efficiency and success rate in next engagements 
• Provide technical support, when developing business case for process improvement projects.
• Provide mentorship to junior engineers

Job Requirements

• Requires a BS and 5+ or MS in EE with 3+ years of industry related experience in design and EDA (Digital Implementation/Signoff)
• Understands ASIC Design implementation process and steps
• Strong hands-on experience with Place & Route (Innovus, ICC2, Fusion Compiler)
• Exposure and experience with Synthesis (Genus, RTL Compiler, Design Compiler)
• Experience with EDA tools in the IC digital implementation & signoff flows (STA tools)
• Strong STA and SDC debugging abilities are required.
• Low power analysis, Clock design/analysis and hands-on 7/5nm technology node experience a plus.
• Automation skills using Perl, Tcl and shell scripting essential 
• Strong analytical & analysis skills covering digital implementation is critical. 
• Proven track record and experience working in a fast paced environment 
• Excellent customer interaction & presentation skills

Be proud and passionate about the work you do. Together, our One Cadence -- One Team culture drives our success. 

#LI-MA1

The annual salary range for California is $98,000 to $182,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Design and analyze packages for RF and mixed-signal heterogenous designs.

Cadence offers amazing opportunities to grow, no matter where you are in your career.

Position involves:

• Implement packaged designs for heterogenous and 3DIC applications
• Work within a team environment to learn, develop and document new process flows
• Support adoption and proliferation of flow at new and existing customers

• Support R&D for tool and methodology improvements
• Create and contribute technical content for Cadence Online Support

Position Requirements:

• Bachelor’s degree with at least 4 years of design/EDA experience or Master’s degree with at least 2 years of experience. Master’s degree preferred      
• At least 2 years of experience in package layout design
• Minimum of 1 year experience in RF package layout design
• Some experience with Virtuoso. VRF/VMT process flow preferred
• Linux or Unix experience
• Computer Languages: TCL, Python or SKILL programming a plus
• Excellent debug skills
• Strong customer-facing communication and problem solving skills
• Strong personal drive for continuous learning and expanding professional skill sets
• Excellent verbal and written communication skills

Familiar with EDA tool operation, setup and debug:

• Design: Allegro Package Designer, Virtuoso
• Simulators: Spectre

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Develop advanced functionalities for Cadence's industry-leading CFD (Computational Fluid Dynamics) software suite. Responsibility includes maintaining and enhancing Cadence Fidelity CFD solver, for automotive and turbomachinery applications.

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Responsibilities
•    Be part of the product engineering team working on Power Noise Reliability analysis platform within Multiphysics Systems BU at Cadence.
•    Build domain expertise in power integrity , 3DIC analysis & optimization , Industry’s first AI driven IR mitigation & fixing methodology , electrothermal optimization for digital designs.
•    Work closely with R&D to facilitate the development of these methodologies and flows.
•    Responsibilities also including supporting strategic customers and functional product engineering driving solutions in the Multiphysics space.

Qualifications
•    Bachelor’s Degree in Electrical / Electronics / Electronics and Communication / VLSI Engineering with 5-7 years related experience
•    OR Masters with 3-4 years of related experience
•    OR PhD with 1 years of related experience

Experience and Technical Skills required
•    3-7 years relevant industry experience in EMIR analysis, PDN analysis with digital signoff tools and Digital Physical implementation as designer or methodology/flow expert.
•    Strong background in Digital logic Design, CMOS logic Design, Power IR drop analysis, Circuit Design and Analysis, Digital and Behavioral simulation fundamentals related to IC and Package Design.
•    Debugging of Low power and multiple power domain analysis for chip power integrity sign-off.
•    Experience with 3DIC design and methodologies is a plus.
•    Must have excellent debugging skills and ability to separate out the critical issues from trivial ones.
•    Ability to solve interface level problems emanating from IC Implementation side and System analysis side.
•    Ability to debug Timing and thermal issues in relation to IR and EM is a plus.
•    Knowledge on TCL, Perl or Python scripting.

Behavioral skills required
•    Must possess strong written, verbal and presentation skills.
•    Ability to establish a close working relationship with both customer peers and management.
•    Explore what’s possible to get the job done, including creative use of unconventional solutions.
•    Work effectively across functions and geographies.
•    Push to raise the bar while always operating with integrity.
 

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are seeking a Principal Software Engineer to join the Voltus team. As a Principal Software Engineer, you will develop and maintain the Voltus Infrastructure, specifically Atlas, the distributed computation platform, ensuring its reliability, scalability, and performance. 
 

Responsibilities:
•    Design, develop, and maintain a robust distributed computation platform to handle large-scale data processing efficiently.
•    Collaborate with cross-functional R&D teams to gather requirements, generate specifications, and architect solutions.
•    Conduct peer code reviews, mentor junior engineers, and contribute to the continuous improvement of development processes and best practices.
•    Troubleshoot and resolve complex distributed computation issues.

Minimum qualifications:
•    BS degree in Computer Science, Computer Engineering, or related field, 7+ years of industry experience 
•    Strong programming skills in C++ (C++11) and Python 3 with a deep understanding of data structures, algorithms, asynchronous and multi-threaded programming.
•    Proficiency in the Linux environment and shell scripting.
•    Experience with designing and debugging large scale distributed systems.
•    Strong verbal and written communication skills.

Desired qualifications:
•    Experience with C++20.
•    Experience with Rust and Go is a plus.
•    Experience using and creating Conan packages.

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This opening is intended to fill a product engineering position on the CFD team with an emphasis on the Fidelity Pointwise software. This position involves the following responsibilities, as they pertain to Pointwise:

1.) Working with sales, application engineers, and developers to create specifications for new software features.

2.) Managing the backlog of requests to assign an appropriate priority level to bug fixes and new feature developments.

3.) Managing the release process to ensure that the software is released on time and contains the enhancements that were planned.

4.) Providing testing and documentation in support of new software releases.

5.) Providing second level support to end users of the software.

Requirements:

•    BS in Mechanical Engineering/Aerospace Engineering (or related degree) + 3 years of relevant experience or MS in Mechanical/Aerospace Engineering (or related degree)
•    Proficiency in unstructured and structured grid generation on industrial applications relevant to the aerospace industry
•    Working knowledge of Linux and high performance computing systems
•    General understanding of numerical methods used in CFD and their associated meshing requirements 
•    Strong technical background in fluid mechanics and aerodynamics
•    Knowledge of geometry repair and editing techniques
 

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The position involves:

• Interfacing with customers regarding library development methodologies, including:
  • timing characterization,
  • EMIR view generation
  • Physical view generation (LEF, GDS, abstracts, etc)
  • Logical view generation (LIB, CDL, Spectre, etc)
  • Technology LEF creation for digital tools
• scoping the level of effort, performing library characterization, generating logical and physical views such as PGV, Verilog, LEF, DSPF, etc and supporting validation of the results
• Supporting adoption and proliferation at existing customers (on/offsite), to help drive business for our library development tools
• Working closely with R&D on tools and methodology improvements
• Create and contribute technical content for Cadence Online Support
• Other digital P&R tasks as needed by the group

Position Requirements:

• Bachelor’s degree with at least 3-7 years of design/EDA experience or Master’s degree with at least 4 years of experience. Master’s degree preferred.
• Knowledge of standard cell and IO characterization methodology
• Excellent analog simulation and debug skills
• Experience with reliability simulation and aging effects
• Understanding of Liberty (.lib), Verilog & other views, such as NLDM, CCS & ECSM
• Strong knowledge of Digital Design Fundamentals, Semiconductor Fundamentals and Static Timing Analysis
• Prior experience with ASIC digital implementation flows and EDA tools is required; Experience with advanced nodes (7nm and below) preferred.
• Good programming knowledge in Unix, Shell scripting, perl and importantly TCL
• Strong customer-facing communication and problem solving skills
• Strong personal drive for continuous learning and expanding professional skill sets
• Excellent verbal and written communication skills

Familiar with EDA tool operation, setup and debug:

• Characterization : Liberate, Liberate MX, Liberate AMS
• Simulators: Spectre, AMS, Xcelium
• Digital: Genus, Innovus, Tempus, Voltus, PrimeTime etc

The annual salary range for California (Other than San Jose) is $108,500 to $201,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are seeking  talented  Application Engineers dedicated for physical design in Cadence Korea. You will be responsible for the physical design implementation projects.

• The candidate will perform the physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.
• The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed designs at the latest technology nodes.
• The responsibility of the candidate includes participating in or leading next generation physical design, methodology and flow development.
• The candidate will work closely with RTL design team to ensure successful tapeouts.

This position requires:

• BS/MS in EE/CS with 6~10 years of hands-on experience in physical design and verification.
• Experienced with ASIC design flow, hierarchical physical design strategies, methodologies, and understand deep sub-micron technology issues.
• Solid knowledge on Low Power Design, DFT, static timing analysis and closure, data skew balancing, duty cycle adjustment, EM/IR-Drop/crosstalk analysis, formal verification, physical verification, DFM and P&R.
• Able to assume responsibility for a variety of technical tasks and to work independently
• Able to be hands-on at all levels of design, with the ability to verify, test, and characterize own designs
• Self-motivated, able to work as a team player, and good English communication skills

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