Total 16 job vacancies by Omnivision Technologies Singapore Pte. Ltd.

Responsibilities

• Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)
• Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation
• Verify Logic at ISP level and Digital System level
• Optimize Design for less gate count and low power consumption
• Drive ISP Design activities in close collaboration with ISP Algorithm Team

Requirements

• Minimum MSEE, or BSEE, or equivalent, plus 3+ years of Digital Design and verification related experience
• Experience / knowledge in CMOS Image Sensor and Image Signal Processing (ISP)
• Experience / knowledge in System C/C++, System Verilog, and Catapult HLS tool.
• Strong debugging and problem-solving skills
• Good communication and interpersonal skills
• Result oriented and embrace change behaviours

Responsibilities

• Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)
• Verify Logic at ISP level and Digital System level
• Optimize Design for less gate count and low power consumption
• Drive ISP Design activities in close collaboration with ISP Algorithm Team

Requirements

• Minimum MSEE, or BSEE, or related/equivalent discipline
• Experience / knowledge in RTL, C/C++ programming and verification
• Strong debugging and problem-solving skills
• Good communication and interpersonal skills
• Result oriented and embrace change behaviours
• C++/SystemC knowledge with High Level Synthesis experience is a plus.
• Experience / knowledge in CMOS Image Sensor is a plus

Responsibilities

• Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)
• Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation
• Verify Logic at ISP level and Digital System level
• Optimize Design for less gate count and low power consumption
• Drive ISP Design activities in close collaboration with ISP Algorithm Team, ISP Design leaders in other sites, and Digital System Design Team
• Leading, supervising and mentoring a team of RTL design engineers

Requirements

• Minimum MSEE, or BSEE, or equivalent, plus 7+ years of Digital Design and verification related experience
• 3+ years project management / people management experience / skill
• Experience / knowledge in CMOS Image Sensor and image signal processing (ISP)
• Experience / knowledge in System C/C++, System Verilog, and Catapult HLS tool.
• Ability to lead teams and collaborate effectively with people in different functions
• Strong time management skills to ensure timely completion of deliverables
• Good communication and interpersonal skills
• Result oriented and embrace change behaviours

Position Overview:

You would be part of a dynamic digital SoC design team that develops state-of-the-art video processing, neural processing, advanced video analytics accelerators, and the entire Camera Processor SoC. You would be joining the team to explore, evaluate and define innovative design SoC architectures, to meet or exceed the technical requirements of the SoC. You would be responsible for the successful implementation of the designs in Verilog/SystemVerilog coding, metrics measurement to meet key objectives & results, and follow-through in comprehensive verifications to successful silicon.

Requirements:

1. Experience in SoC architecture and design, and RTL coding with Verilog/SystemVerilog

2. Experience in ARM, RISC processor system

3. Experience in embedded C and assembly code programming

4. Experience in analysis of power, timing and area

5. Experience in at least one of scripting languages (e.g. Perl, Python, TCL, or Bash)

6. Disciplined, quality-minded, and highly driven for excellence

7. Excellent team player and good communication skills

8. MSEE/BSEE in Electrical Engineering or Computer Engineering

9. Candidates with relevant experiences would be offered as Staff, taking on higher responsibilities

10. Experience in always-on system, automotive system, secured system, bus interconnect, neural processing, video processing and video analytics is a plus

11. Experience in system modelling and simulation using emulator and SystemC is a plus

12. Passionate and strong in general programming is a plus

Position Overview:

As design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. The goal is simple – to achieve zero-defect with the best and smartest approach to the large verification space.

Requirements:

1. Experience in UVM verification methodology

2. Disciplined, quality-minded, and highly driven for excellence,

3. Excellent team player and good communication skills

4. MSEE/BSEE in Electrical Engineering or Computer Engineering, with 3 years of relevant experience, but are open to fresh graduates with outstanding results

5. Candidates with relevant experiences would be offered as Senior or Staff, taking on higher responsibilities

6. Experience in video processing and video analytics is a plus

7. Passionate and strong in general programming is a plus

Responsibilities

• Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)
• Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation
• Verify Logic at ISP level and Digital System level
• Optimize Design for less gate count and low power consumption
• Drive ISP Design activities in close collaboration with ISP Algorithm Team

Requirements

• Minimum MSEE, or BSEE, or equivalent, plus 3+ years of Digital Design and verification related experience
• Experience / knowledge in CMOS Image Sensor and Image Signal Processing (ISP)
• Experience / knowledge in System C/C++, System Verilog, and Catapult HLS tool.
• Strong debugging and problem-solving skills
• Good communication and interpersonal skills
• Result oriented and embrace change behaviours

Responsibilities

• Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)
• Verify Logic at ISP level and Digital System level
• Optimize Design for less gate count and low power consumption
• Drive ISP Design activities in close collaboration with ISP Algorithm Team

Requirements

• Minimum MSEE, or BSEE, or related/equivalent discipline
• Experience / knowledge in RTL, C/C++ programming and verification
• Strong debugging and problem-solving skills
• Good communication and interpersonal skills
• Result oriented and embrace change behaviours
• C++/SystemC knowledge with High Level Synthesis experience is a plus.
• Experience / knowledge in CMOS Image Sensor is a plus

Responsibilities

• Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)
• Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation
• Verify Logic at ISP level and Digital System level
• Optimize Design for less gate count and low power consumption
• Drive ISP Design activities in close collaboration with ISP Algorithm Team, ISP Design leaders in other sites, and Digital System Design Team
• Leading, supervising and mentoring a team of RTL design engineers

Requirements

• Minimum MSEE, or BSEE, or equivalent, plus 7+ years of Digital Design and verification related experience
• 3+ years project management / people management experience / skill
• Experience / knowledge in CMOS Image Sensor and image signal processing (ISP)
• Experience / knowledge in System C/C++, System Verilog, and Catapult HLS tool.
• Ability to lead teams and collaborate effectively with people in different functions
• Strong time management skills to ensure timely completion of deliverables
• Good communication and interpersonal skills
• Result oriented and embrace change behaviours

Responsibilities

• Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)
• Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation
• Verify Logic at ISP level and Digital System level
• Optimize Design for less gate count and low power consumption
• Drive ISP Design activities in close collaboration with ISP Algorithm Team, ISP Design leaders in other sites, and Digital System Design Team
• Leading, supervising and mentoring a team of RTL design engineers

Requirements

• Minimum MSEE, or BSEE, or equivalent, plus 7+ years of Digital Design and verification related experience
• 3+ years project management / people management experience / skill
• Experience / knowledge in CMOS Image Sensor and image signal processing (ISP)
• Experience / knowledge in System C/C++, System Verilog, and Catapult HLS tool.
• Ability to lead teams and collaborate effectively with people in different functions
• Strong time management skills to ensure timely completion of deliverables
• Good communication and interpersonal skills
• Result oriented and embrace change behaviours

Position Overview:

You would be part of a dynamic digital SoC design team that develops state-of-the-art video processing, neural processing, advanced video analytics accelerators, and the entire Camera Processor SoC. You would be joining the team to explore, evaluate and define innovative design SoC architectures, to meet or exceed the technical requirements of the SoC. You would be responsible for the successful implementation of the designs in Verilog/SystemVerilog coding, metrics measurement to meet key objectives & results, and follow-through in comprehensive verifications to successful silicon.

Requirements:

1. Experience in SoC architecture and design, and RTL coding with Verilog/SystemVerilog

2. Experience in ARM, RISC processor system

3. Experience in embedded C and assembly code programming

4. Experience in analysis of power, timing and area

5. Experience in at least one of scripting languages (e.g. Perl, Python, TCL, or Bash)

6. Disciplined, quality-minded, and highly driven for excellence

7. Excellent team player and good communication skills

8. MSEE/BSEE in Electrical Engineering or Computer Engineering

9. Candidates with relevant experiences would be offered as Staff, taking on higher responsibilities

10. Experience in always-on system, automotive system, secured system, bus interconnect, neural processing, video processing and video analytics is a plus

11. Experience in system modelling and simulation using emulator and SystemC is a plus

12. Passionate and strong in general programming is a plus

Position Overview:

As design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. The goal is simple – to achieve zero-defect with the best and smartest approach to the large verification space.

Requirements:

1. Experience in UVM verification methodology

2. Disciplined, quality-minded, and highly driven for excellence,

3. Excellent team player and good communication skills

4. MSEE/BSEE in Electrical Engineering or Computer Engineering, with 3 years of relevant experience, but are open to fresh graduates with outstanding results

5. Candidates with relevant experiences would be offered as Senior or Staff, taking on higher responsibilities

6. Experience in video processing and video analytics is a plus

7. Passionate and strong in general programming is a plus

Responsibilities

· Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)

· Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation

· Verify Logic at ISP level and Digital System level

· Optimize Design for less gate count and low power consumption

· Drive ISP Design activities in close collaboration with ISP Algorithm Team

Requirements

· Minimum MSEE, or BSEE, or equivalent, plus 3+ years of Digital Design and verification related experience

· Experience / knowledge in CMOS Image Sensor and image signal processing (ISP)

· Experience / knowledge in System C/C++, System Verilog, and Catapult HLS tool.

· Strong debugging and problem-solving skills

· Good communication and interpersonal skills

· Result oriented and embrace change behaviours

Responsibilities

· Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)

· Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation

· Verify Logic at ISP level and Digital System level

· Optimize Design for less gate count and low power consumption

· Drive ISP Design activities in close collaboration with ISP Algorithm Team

Requirements

· Minimum MSEE, or BSEE, or equivalent, plus 3+ years of Digital Design and verification related experience

· Experience / knowledge in CMOS Image Sensor and image signal processing (ISP)

· Experience / knowledge in System C/C++, System Verilog, and Catapult HLS tool.

· Strong debugging and problem-solving skills

· Good communication and interpersonal skills

· Result oriented and embrace change behaviours

Responsibilities

· Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)

· Verify Logic at ISP level and Digital System level

· Optimize Design for less gate count and low power consumption

· Drive ISP Design activities in close collaboration with ISP Algorithm Team

Requirements

· Minimum MSEE, or BSEE, or related/equivalent discipline

· Experience / knowledge in RTL, C/C++ programming and verification

· Strong debugging and problem-solving skills

· Good communication and interpersonal skills

· Result oriented and embrace change behaviours

· C++/SystemC knowledge with High Level Synthesis experience is a plus.

· Experience / knowledge in CMOS Image Sensor is a plus

Responsibilities

· Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)

· Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation

· Verify Logic at ISP level and Digital System level

· Optimize Design for less gate count and low power consumption

· Drive ISP Design activities in close collaboration with ISP Algorithm Team, ISP Design leaders in other sites, and Digital System Design Team

· Leading, supervising and mentoring a team of RTL design engineers

Requirements

· Minimum MSEE, or BSEE, or equivalent, plus 7+ years of Digital Design and verification related experience

· 3+ years project management / people management experience / skill

· Experience / knowledge in CMOS Image Sensor and image signal processing (ISP)

· Experience / knowledge in System C/C++, System Verilog, and Catapult HLS tool.

· Ability to lead teams and collaborate effectively with people in different functions

· Strong time management skills to ensure timely completion of deliverables

· Good communication and interpersonal skills

· Result oriented and embrace change behaviours