Total 15 job vacancies by Western Digital

• Bachelors or Masters in Electronics/Electrical Engineering
• Minimum 4+yrs of experience in ASIC/IP Digital Design for large SOCs
• Expertise in implementation of RTL in Verilog/SV for complex designs with multiple clock domains
• Expertise with various bus matrices on AHB, AXI and NOC designs
• Working knowledge of at-least one of the protocols like UFS/PCIe/SAS/SATA/USB
• Experience in ARM processor and/or NAND Flash subsystems would be a plus
• Experience in low power design methodology and clock domain crossing designs
• Experience in Spyglass Lint/CDC checks, report analysis and signoff
• Experience in Synthesis using DC, timing analysis and closure would be a plus
• Experience of UPF flow, defining constraints working with PD teams
• Expertise in Perl, Python, TCL language is a plus
• Ability to ramp-up quickly and work cohesively with Verification/Validation teams
• Must have a good attitude and be solution-oriented
• Excellent written and verbal communication skills

• Coding, debugging, and integrating firmware, as well as the integration, regression, and requirement testing of complex SW/HW/ASIC systems
• Analyze requirements to determine the feasibility of design and schedule
• Consult with ASIC/HW/FW engineers to evaluate interface between hardware and firmware, and operational and performance requirements of the overall system
• Develop firmware testing along with firmware development

n this position, you will develop advanced system architectures and complex simulation models for Western Digital’s next generation solid state drive products.  You will need to initiate and analyze changes to the architecture of the product.  Typical activities include designing, programming, debugging, and modifying simulation models in order to evaluate these changes and assess the performance, power, and endurance of the product.

You will work closely with excellent colleague engineers, cope with complex challenges, innovate, and develop products that will be sold in millions of units.

• Bachelors or Masters in Electronics/Electrical Engineering
• Minimum 3+yrs of experience in ASIC/IP Digital Design for large SOCs
• Expertise in implementation of RTL in Verilog/SV for complex designs with multiple clock domains
• Expertise with various bus matrices on AHB, AXI and NOC designs
• Working knowledge of at-least one of the protocols like UFS/PCIe/SAS/SATA/USB
• Experience in ARM processor and/or NAND Flash subsystems would be a plus
• Experience in low power design methodology and clock domain crossing designs
• Experience in Spyglass Lint/CDC checks, report analysis and signoff
• Experience in Synthesis using DC, timing analysis and closure would be a plus
• Experience of UPF flow, defining constraints working with PD teams
• Expertise in Perl, Python, TCL language is a plus
• Ability to ramp-up quickly and work cohesively with Verification/Validation teams
• Must have a good attitude and be solution-oriented
• Excellent written and verbal communication skills

This position is for Project lead for next generation controllers. The following are required skills

1. Project end to end delivery experience, the candidate needs to have complete design quality check experience. Includes tracking Architecture to GDS deliveries.

2. Productization experience with NAND flash controllers

3. Experience with Automotive compliance processes like DFMEA, FMEDA

As the Linux/Unix architect, you will play a critical role in ensuring the optimal performance, reliability, and security of our IT infrastructure. The ideal candidate will have extensive experience with AIX, Red Hat, CentOS, Ubuntu, and Solaris. This role involves the installation, configuration, maintenance, and troubleshooting of our IT systems, along with implementing security best practices and providing technical support. Success in this position requires strong problem-solving skills, technical expertise, effective communication, and a proactive approach to infrastructure management and security.

ASIC Power Architect - Job Description

We are seeking a highly skilled and experienced ASIC Power Architect to join our dynamic team responsible for SoC Architecture of next-generation of Flash Controllers.

As an ASIC Power Architect, you will be responsible for defining Multi Power Domain architectures in SoC, with a particular focus on Low-Power states.

The ideal candidate will have a deep understanding of SoC development flow, power management, and the ability to drive architecture convergence to deliver high-performance, low-power, and cost-effective solutions.

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• Power Analysis based on RTL/Netlist including early power estimation based on previous generation architectures
• Power Optimization techniques at various phases on Design & Development
• Defining Methodologies and Processes for next generation power aware design, development and implementation
• Working closely with and guiding PD implementation from Power optimization perspective
• Characterization process / data analysis with emphasis on Voltage scaling methodologies – SVS / DVFS / DVS and binning
• Leading complex activities while having multiple interfaces
• Collaborate with cross-functional teams to define and refine Power Architecture, ensuring alignment with industry standards and customer needs.
• Working closely with the Design, Verification, DFT and Physical Design teams while guiding them.
• Evaluate all aspects of the ASIC power management from requirements, through definition phase, Design, Verification and to Synthesis, Place and Route, Timing and Power optimizations.

SKILLS:

• Extensive experience in SoC architecture, Power Management and full ASIC flow.
• Solid understanding of Power Management techniques and Low-Power design principles.
• Physical Understanding on latest Process technologies N7 & N5
• Hands on in Silicon debug of complex power issues
• Proficiency in Low-Power standards like UPF/CPF.
• Working knowledge on UPF based RTL / PGPIN simulations.
• Proficiency in ASIC design tools, simulation methodologies, and hardware description languages (HDLs).
• Excellent analytical and problem-solving skills with a focus on power optimization.
• Strong communication skills and the ability to work effectively in cross-functional teams.

SOC Design Engineer  - Job Description

You should have strong knowledge and experience with all aspects of the SOC design and implementation flow – including datapath design, low power design, clock and reset schemes, coverage driven verification, synthesis, P&R, STA, DFT, power-islands, floor-planning, CTS, IR-drop – and an understanding of how architecture decisions impact these flows. You will be responsible for developing, contributing, and leading ASIC macro and micro-architecture activities in our storage-based controllers. You should be highly motivated with strong communication skills, attention to detail, and quality oriented. Candidates with a take-ownership attitude will succeed in this role.

it is a hands-on SOC design implementation role.

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• Strong knowledge in IP/SOC design methodologies.
• Sound knowledge of RTL/SOC design/integration with Verilog/system Verilog
• Strong experience in Synthesis, timing, full chip netlist & front-end design tools& flows Low power design
• Mentoring juniors and enhancing their skill set
• Expert knowledge on code coverage, functional coverage, Lint, CDC etc
• Power Analysis based on RTL/Netlist including early power estimation based on previous generation architectures
• Defining requirements for ASIC design, verification, and physical implementation teams
• Evaluating area, performance, power, and ease-of-implementation trade-offs between different implementation solutions
• Reviewing and configuring 3rd party IPs
• Supporting other teams in the ASIC organization and reviewing their work
• Supporting product teams with documentation, code-reviews, and silicon debug
• Continuously finding opportunities for improving design quality and design practices
•  

Job Summary:

We are seeking an experienced STA Architect to lead our technical team. The ideal candidate will have extensive experience in Static Timing Analysis, a deep understanding of digital design, and the ability to lead and mentor a team of engineers.

This role requires hands-on expertise in STA tools, methodologies, and a strategic vision to drive the timing closure of complex designs.

Key Responsibilities:

- Lead the STA function and oversee all aspects of timing analysis and closure for ASIC designs.

- Develop and implement STA methodologies and best practices to ensure high-quality design closure.

- Collaborate with cross-functional teams, including IP design, DFT,  and verification teams, to address timing challenges and drive design convergence.

- Conduct thorough timing analysis using industry-standard STA tools (e.g., Synopsys PrimeTime, Cadence Tempus).

- Define and drive timing constraints development and validation processes.

- Provide technical leadership and mentorship to junior engineers, fostering a culture of continuous learning and innovation.

- Work closely with project managers to ensure timely delivery of design milestones and project goals.

- Stay updated with the latest industry trends and advancements in STA methodologies and tools.

- Participate in design reviews, providing expert insights and recommendations to optimize performance and timing.

- Troubleshoot and resolve complex timing issues, utilizing advanced debugging techniques.

Position Overview:

We are seeking a highly skilled and experienced Physical Design Implementation Lead with a strong background in Static Timing Analysis (STA) to join our dynamic team. The ideal candidate will have a proven track record in leading physical design projects, a deep understanding of STA methodologies, and the ability to drive successful implementation of complex integrated circuits.

Key Responsibilities:

- Lead the physical design implementation efforts for advanced semiconductor designs, ensuring project milestones and quality standards are met.

- Perform and oversee static timing analysis to ensure timing closure of high-performance digital designs.

- Collaborate with cross-functional teams, including RTL design, DFT, and verification, to define and optimize design constraints and methodologies.

- Develop and execute detailed floorplanning, placement, routing, and optimization strategies.

- Conduct design reviews and provide technical guidance to team members on physical design and STA-related issues.

- Implement power, performance, and area (PPA) optimization techniques to achieve design goals.

- Debug and resolve complex design and timing issues using industry-standard EDA tools.

- Stay updated with the latest advancements in physical design and STA tools and methodologies, and incorporate them into the design flow.

We are looking for an Oracle Cloud Security Architect  with focus on Oracle fusion ERP  security. In this role you will lead a team to support Oracle fusion ERP to be compliant with Western Digital's policy and controls while enabling privilege access for its users.

Responsibilities

• Manage Security in Oracle cloud ERP, OTM (Oracle transport management), PEGA, Lease Accelerator and Oracle EBS applications.
• Analyze business processes and documenting user role requirements, create technical security role design documents.
• Requirement gathering and implementing security and access control, Role design for oracle cloud ERP modules such as Finance, Order to Cash, Supply Chain.
• Co-Facilitate design workshops, access controls and SOD's.
• Manage Service vendors when implementing oracle cloud ERP projects.
• Manage System refresh activities in Production and Non Prod environments
• Assist in License management and License optimization for Oracle Cloud ERP
• Support external and internal audit requirements. Provide evidence, clarifications and implement controls.
• Possess fundamental understanding of Oracle ERP security and administrative components (Responsibilities, Profile Options, Menus, RBAC Grants, form personalization, etc.) and security administration concepts such as least privilege access, segregation of duties.
• Perform SOC 1 and SOC 2 (Service Organization controls) Report review of vendor systems.
• Perform SOD and SOX analysis at both user and role levels.
• Manage team of oracle cloud administrators by guiding them in ticket resolution and meeting SLA (Service level agreements).
• Building of accelerators and tools to expedite SOD analysis and remediation steps.          
• Assist IT Compliance team in ITGC and Business process control testing.
• Assist in SOAK testing and RPA automation of tasks in oracle cloud ERP environments.

The FPGA design-verification team, part of the (VHS) group is responsible for developing a wide range of FPGA solutions for post-silicon validation of memory devices across Western Digital.

 Your main responsibilities as part of a winning group:

• Complex logic blocks & IPs design verification 
• Work in a multi-disciplinary environment with a variety of complex interfaces.

We are seeking a highly skilled and experienced ASIC Power Architect to join our dynamic team responsible for SoC Architecture of next-generation of Flash Controllers.

As an ASIC Power Architect, you will be responsible for defining Multi Power Domain architectures in SoC, with a particular focus on Low-Power states.

The ideal candidate will have a deep understanding of SoC development flow, power management, and the ability to drive architecture convergence to deliver high-performance, low-power, and cost-effective solutions.

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• Power Analysis based on RTL/Netlist including early power estimation based on previous generation architectures.
• Power Optimization techniques at various phases on Design & Development
• Defining Methodologies and Processes for next generation power aware design, development and implementation
• Working closely with and guiding PD implementation from Power optimization perspective
• Characterization process / data analysis with emphasis on Voltage scaling methodologies – SVS / DVFS / DVS and binning
• Leading complex activities while having multiple interfaces
• Collaborate with cross-functional teams to define and refine Power Architecture, ensuring alignment with industry standards and customer needs.
• Working closely with the Design, Verification, DFT and Physical Design teams while guiding them.
• Evaluate all aspects of the ASIC power management from requirements, through definition phase, Design, Verification and to Synthesis, Place and Route, Timing and Power optimizations.

Job-Title: STA/Synthesis
Responsibilities:
· In this position, the individual will be responsible for complete ownership of full chip  low power methodology and signoff for high performance designs, development-debug of UPF and CLP convergence and closure.
· Additional responsibilities include proactively working with the DFT teams and EDA vendors to assess best in class tools / capability and benchmark them to drive compelling adoption arguments.
· He / She will also drive IP integration strategies that ensure quality ASICs and avoid schedule surprises.
· The individual will influence next generation synthesis and physical design implementation capability to meet the demands of the ASIC design road map.
· Ability to work with minimal supervision and drive to exceed expectations is a plus.
· Hands on direct experience in Synthesis with emphasis on STA and Low Power design.
· Proficiency in understanding and writing Verilog, System Verilog RTL, STA closure and experience in PERL/TCL/Shell scripting is a must.
· The individual must have proven hands on experience on multiple low power hierarchical and flat ASICs at 28/16/7 nm designs.
· Expertise in Design Compiler is a must. Experience with DFT Compiler, RTL Compiler and Conformal is a PLUS.
· Good verbal and written communication skills are required.

As a System Validation Engineer in Automotive SSD group at Western Digital, you will develop test cases and infrastructure to validate the system design for Solid State Drives using NAND Flash memory. This involves designing automated white/grey/black-box tests to exercise firmware functionality for new high-performance mass storage controllers. Your tests will be used to verify feature functionality, reliability, endurance, and performance requirements of Solid-State Drives for the client market. You can expect to work closely with fellow firmware verification engineers, firmware developers, Memory system design engineer, Memory system validation engineers, Architecture and system hardware design engineers, product development engineers and production engineers to solve cross-functional design issues.